1. Field of the Invention
The present invention relates to a cache memory circuit for use between a main memory and a request source such as a central processing unit and in particular, to a cache control circuit in such a cache memory circuit.
2. Description of the Prior Art
A cache memory circuit is used between a main memory and a central processing unit in a high speed information processing system and holds temporarily those portions of the contents of the main memory which are currently used by the central processing unit. The cache memory is a small and high speed buffer memory and therefore, an access time for the cache memory is quite less than that for the main memory. Therefore, the central processing unit spends a reduced waiting time for data such as instructions and operands to be fetched and/or stored.
On the other hand, the formation processing system uses the logical or virtual addressing method. In the case, the central processing unit issues a logical address together with a read/write request. Accordingly, the cache memory circuit is associated with an address conversion circuit for converting the logical address into a physical or real address on the main memory
The logical address issued from the central processing unit comprises a first logical address portion such as a logical page address and a second logical address portion such as a logical line address. The first address portion is converted into a first physical address portion by the address conversion circuit, and the converted first physical address portion is supplied to the cache memory circuit. The second logical address portion is directly applied to the cache memory circuit as a second physical address portion without address conversion. When receiving the first and the second physical address portions, the cache memory circuit starts to write/read operation for a cache memory or a data memory under control of a cache control circuit in the cache memory circuit after deciding whether or not data are held in the cache memory which are corresponding to the physical address comprising a pair of the first physical address portion and the second physical address portion as received.
When the address conversion circuit cannot convert the first logical address portion because of absence of the first physical address portion corresponding to the first logical address portion, the address conversion circuit produces a mismatch signal. The mismatch signal is delivered to the central processing unit and the cache memory circuit. Then, the central processing unit decides the present write/read request invalid while the cache memory circuit is prevented by the mismatch signal from starting the write/read operation for the cache memory.
In a case where the address conversion circuit is not desired to be formed together with the cache memory circuit in a chip of an integrated circuit because of an increased cost of the integrated circuit chip, the address conversion circuit is provided as an integrated circuit chip separated from a chip having the cache memory circuit. In use of the address conversion circuit of the separate type which will be referred to as the address conversion unit, it takes a comparatively long time to issue the mismatch signal from the address conversion unit and also to decide the mismatch signal at the cache control circuit. As a result, an unignorable waiting time is spent until the cache memory unit starts the read/write operation after reception of the control signal from the central processing unit. This does not mean that the high speed performance of the central processing unit is fully utilized.